Non-volatile semiconductor memory devices electrically erase and store data. They conserve data even if power is not supplied to the memory devices, and thus are increasingly applied to various industries including mobile communication systems and memory cards.
Among non-volatile memory devices, flash memory devices operate a program for each cell, and erase data for each block or sector. Since flash memory devices use a conductive material, such as doped polysilicon, as a floating gate material, parasitic capacitance between neighboring gate structures is increased with high integration. To solve this problem of flash semiconductor memory devices, a non-volatile semiconductor memory device called a metal-oxide-insulator-oxide-semiconductor (MOIOS) memory device, such as an silicon-oxide-nitride-oxide-semiconductor (SONOS) memory device or a metal-oxide-nitride-oxide-semiconductor (MONOS) memory device, has been developed. The SONOS memory device uses silicon as a control gate material, and the MONOS memory device uses metal as a control gate material.
MOIOS memory devices use a charge trap layer, such as a silicon nitride film, instead of a floating gate as a unit to store electric charges. That is, MOIOS memory devices replaces a stack (including a floating gate and insulating layers stacked over the upper and lower surfaces thereof), formed between a substrate and a control gate in a memory cell of a flash semiconductor memory device, with an oxide-nitride-oxide (ONO) stack including an oxide film, a nitride film, and an oxide film, sequentially stacked. MOIOS memory devices use a property that a threshold voltage is shifted by trapping electric charges in the nitride film.
MOIOS memory devices may be formed as a stack gate type, a split gate type, or a combination type thereof. In a split gate type SONOS memory devices, characteristics of a cell may be influenced by the length of the nitride film. Split gates may be formed by sequentially depositing an oxide film, a nitride film, and an oxide film over a substrate and etching the deposited oxide film, nitride film, and oxide film using a photoresist pattern. Here, an overlay variation in the photolithography to form the photoresist pattern may generate a difference in the lengths of the split gates.
FIGS. 1A to 1B are longitudinal-sectional views illustrating a process of forming SONOS split gates. As shown in FIG. 1A, an ONO layer, i.e., a first oxide film 110, a nitride film 120, and a second oxide film 130 are sequentially formed over a substrate. Thereafter, a photoresist pattern 140 to form the split gates is formed by carrying out photolithography.
As shown in FIG. 1B, split second oxide films 130-1 and 130-2 and split nitride films 120-1 and 120-2 are formed by etching the second oxide film 130 and the nitride film 120 using the photoresist pattern 140 as a mask. Thereafter, the photoresist pattern 140 is removed.
In the formation of the photoresist pattern 140, as shown in FIG. 1a, misalignment of the photoresist pattern 140 may occur due to a minimal critical dimension of a photo and an overlay variation. When the second oxide film 130 and the nitride film 120 are patterned using the misaligned photoresist pattern 140, there may be a difference between the length L1 of the first split nitride film 120-1 and the length L2 of the second split nitride film 120-2 (for example, L2>L1).
When there is a difference between the length L1 of the first split nitride film 120-1 and the length L2 of the second split nitride film 120-2, the lengths of split charge trap nitride films of memory cells (for example, flash memory cells) are not uniform. Uniformity in the characteristics of the memory cells is reduced, and thus reliability of the semiconductor device may deteriorate.